Capstone projects on VLSI, Jalandhar

Sleepy Keeper Approach for Power Performance Tuning in VLSI Design.
Adiabatic Logic Based Low Power Multiplexer and De-multiplexer.
Low Power D-latch design using MCML Tri-state Buffers.
Low power adiabatic booth multiplier using Positive feedback adiabatic logic (PFAL).
Clock gated 4-bit Johnson counter using low power JK flip flop.

3 bit pattern recognition using Artificial Intelligence.
Design and Simulation of High Speed Frequency Dectector.
Design of FLASH ADC using Threshold Inverter Quantization Technique.
Design and Analysis of Multiplexer based Flash ADC.
Design of CMOS operational Amplifier in Submicron Technology.

Implementation of pipe lined AES algorithm on FPGA (Xilinx) kit.
Image compression technique with discrete wavelete transform technique applied by Verilog for the efficient use of area.
Verilog implementation of RSA cryptography algorithm.
FPGA implementation JPEG 2000 using 2-D DWT .
FPGA implementation of the 12-bit Ternary multiplier.

FPGA-Based Fault Emulation of Synchronous Sequential Circuits
Pragmatic Integration of SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV
Built-in Self-Test Technique for Diagnosis of Delay Faults in Cluster-Based Field Programmable Gate Arrays
ASIC Design of Complex Multiplier
A Low Cost VLSI Implementation for Efficient Removal of Impulse Noise
FPGA Based Space Vector PWM Control IC For Three Phase Induction Motor Drive
VLSI Implementation of Auto Correlator and CORDIC Algorithm for OFDM Based WLAN
Automatic Road Extraction Using High Resolution Satellite Images
VHDL Design for Image Segmentation Using Gabor Filter for Disease Detection
A Low Complexity Turbo Decoder Architecture for Energy Efficient Wireless Sensor Networks
Improvement of The Orthogonal Code Convolution Capabilities Using FPGA Implementation
Design and Implementation of Floating Point ALU
CORDIC Design for Fixed Angle of Rotation
Product Reed-Solomon Codes for Implementing NAND Flash Controller on FPGA Chip
Statistical SRAM Read Access Yield Improvement Using Negative Capacitance Circuits
Power Management of MIMO Network Interfaces on Mobile Systems
Design of Data Encryption Standard for Data Encryption
Low Power and Area Efficient Carry Select Adder
Synthesis and Implementation of UART Using VHDL Codes
Improved Architectures for a Fused Floating-Point Add-Subtract Unit
An FPGA Based 1-Bit All Digital Transmitter Employing Delta-Sigma Modulation with RF Output for SDR
Optimizing Chain Search Usage in The BCH Decoder for High Error Rate Transmission
Digital Design of DS-CDMA Transmitter Using Verilog HDL and FPGA
Design and Implementation of Efficient Systolic Array Architecture
A VLSI-Based Robot Dynamics Learning Algorithm
A Versatile Multimedia Functional Unit Design Using the Spurious Power Suppression Technique
Design of Bus Bridge between AHB and OCP
Behavioral Synthesis of Asynchronous Circuits
Speed Optimization of a FPGA Based Modified Viterbi Decoder
Implementation of I2C Interface
A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique
Clamping Virtual Supply Voltage of Power Gated Circuits for Active Leakage Reduction and Gate Oxide Reliability
FPGA Based Power Efficient Channelizer for Software Defined Radio
VLSI Architecture and FPGA Prototyping of a Digital Camera for Image Security and Authentication
Operation Improvement of Indoor Robot
Design and Implementation of an ON-Chip Permutation Network for Multiprocessor System On-Chip
A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems
DMA Controller (Direct Memory Access ) Using VHDL/VLSI
Reconfigurable FFT Using CORDIC Based Architecture for MIMI-OFDM Receivers
Spurious Power Suppression Technique for Multimedia/DSP Applications
Efficiency of BCH Codes in Digital Image Watermarking
Dual Data Rate SD RAM Controller
Implementing Gabor Filter for Fingerprint Recognition Using Verilog HDL
Design of a Practical Nanometer Scale Redundant via Aware Standard Cell Library for Improved Redundant via 1 Insertion Rate
A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture
A Framework for Correction of Multi-Bit Soft Errors
Viterbi-Based Efficient Test Data Compression
Implementation of FFT/IFFT Blocks for OFDM
Wavelet Based Image Compression by VLSI Progressive Coding
VLSI Implementation of Fully Pipelined Multiplier Less 2d DCT/IDCT Architecture for Jpeg

You may also like...

Leave a Reply

Your email address will not be published. Required fields are marked *