Implementation of pipe lined AES algorithm on FPGA (Xilinx) kit.
Image compression technique with discrete wavelete transform technique applied by Verilog for the efficient use of area.
Verilog implementation of RSA cryptography algorithm.
FPGA implementation JPEG 2000 using 2-D DWT .
FPGA implementation of the 12-bit Ternary multiplier.
3 bit pattern recognition using Artificial Intelligence.
Design and Simulation of High Speed Frequency Dectector.
Design of FLASH ADC using Threshold Inverter Quantization Technique.
Design and Analysis of Multiplexer based Flash ADC.
Design of CMOS operational Amplifier in Submicron Technology.
Sleepy Keeper Approach for Power Performance Tuning in VLSI Design.
Adiabatic Logic Based Low Power Multiplexer and De-multiplexer.
Low Power D-latch design using MCML Tri-state Buffers.
Low power adiabatic booth multiplier using Positive feedback adiabatic logic (PFAL).
Clock gated 4-bit Johnson counter using low power JK flip flop.